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Features
* * * * * * * * * * * * * * * * * *
300 mA/1.9V/2.5V DC to DC for Co-processor Core 80 mA/2.8V Dual-mode LDO for Memories (LDO1) 130 mA/2.7V/2.8V LDO for Camera Module (LDO2) 130 mA/2.8V LDO for Analog Section Supply of Audio Stereo Codec (LDO6) 10 mA/1.8V/2.8V LDO for Digital Section Supply of Audio Stereo Codec (LDO7) 130 mA/2.8V LDO for Analog Section Supply of Bluetooth(R) Module (LDO4) 130 mA/2.8V LDO for Digital Section Supply of Bluetooth(R) Module (LDO5) 2 mA/2.4V/2.7V LDO for Low-power Device Control (LDO3) Open Drain Switch Three-channel Level Shifters LED Driver 0.5 mA/1.5V Bufferized Voltage Reference Power Management Start-up Controller and Reset Generation Over- and Under-voltage Protections Over-temperature Protection Shutdown, Sleep and Enable Modes Straightforward and Easy Interfacing to any Baseband Controller Small 5 mm x 5 mm, 49-ball BGA Package
Power Management for Mobiles (PM) AT73C204
Description
The AT73C204 device provides an integrated power management solution for the addon multimedia features in new-generation mobile phones. These features include a camera module, sound system for polyphonic ringing tones, memory module for downloaded MP3 files, Bluetooth module for cordless headset, etc. The most common approach to the IC architecture of these new-generation mobile phones is a baseband processor for the basic telephony functions and a separate co-processor for the multimedia features. Atmel proposes the AT73C202 for power management of the baseband processor and RF elements, and the AT73C204 for power management of the multimedia features. The AT73C204 is suitable for any telecommunications standard: GSM/GPRS, PDS, CDMA, CDMA2000, WCDMA or UMTS. It is packaged in a small form-factor 49-ball 5 mm x 5 mm BGA package.
6014A-PMGMT-10/03
Functional Block Diagram
Figure 1. AT73C204 Functional Block Diagram
E1 VINF D5 CE Reset Generator RESB F6
C1
LEDI
LED Driver
LEDO
C2
LX G6 D4 G5 VINA DVA DM Oscillator A5 B5 C7 E5 B7 VINB EN2 CREF GNDG VREF SWI SWO GNDD VINC EN4 Open Drain Switch LDO3 2.4V/2.7V/2mA LDO4 2.8V/130mA VR VOUT2 LDO2 2.7V/2.8V/130mA VOUT3 GNDB VOUT4 B4 LDO1 2.8V/130mA VOUT1 B6 DC-DC Converter 1.9V/2.5V 300mA F7 VOUT0 GNDA G4 G7
C5 B3 A4 B3 A4
A6 A7 B1
VOUT5 C4 EN5 LDO5 2.8V/130mA GNDC
A1 A2
D7 E6
VIND EN6
LDO6 2.8V/130mA
VOUT6
E7
G1 G3 F4 E4 F3 G2
VINE EN7 DVB LSI1 LSI2 LSI3 GNDE D1 D3 GNDF C6 Three-channel Level Shifter LSO1 LSO2 LSO3 LDO7 1.8V/2.8V/10mA VOUT7 E3
F1 F2 E2
D6
F5
C3
D2
2
AT73C204
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AT73C204
Pin Description
Table 1. AT73C204 Pin Description
Signal LEDI LEDO VINF Ball C1 C2 E1 Type I O Power Supply Description LED driver input LED driver output Input voltage
Power On Block CE GNDF RES-B GNDG D5 C6 F6 E5 I Ground O Ground Chip Enable Ground Reset open collector output Ground
Baseband Supply Block VINA LX DM VOUTO GNDA VINB EN2 VOUT2 GNDB VOUT1 VREF VOUT3 G6 F7 G5 G4 G7 A5 B5 B4 A7 B6 B7 A6 I O Ground O O O Power Supply O I O Ground Input supply for DC-DC converter DC-DC converter Output Inductor Low-power/Full-power selector DC-DC converter output Ground of DC-DC Converter Input supply for LDO1, LDO2, LDO3 Enable LDO2 LDO2 output voltage Ground for LDO1, LDO2, LDO3 LDO1 output voltage Bufferized voltage reference LDO3 output voltage RF Supply Block VINC EN4 EN5 VOUT4 GNDC VOUT5 A3 B2 C4 B1 A2 A1 Power Supply I I O Ground O Input supply for LDO4, LDO5 Enable LDO4 Enable LDO5 LDO4 output voltage Ground for LDO4, LDO5 LDO5 output voltage
Vibrator and Buzzer Driver Block VIND EN6 VOUT6 SWI SWO D7 E6 E7 C5 B3 Power Supply I O I O LDO6 input supply Enable LDO6 LDO6 output voltage Open drain enable Open drain output
3
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Table 1. AT73C204 Pin Description (Continued)
Signal GNDD Ball A4 Type Ground Description Open drain ground
SIM Interface Block VINE EN7 DVB LSI1 LSI2 LSI3 VOUT7 LSO1 LSO2 LSO3 G1 G3 F4 E4 F3 G2 E3 F1 F2 E2 Power Supply I I I I IO O O O IO LDO7 input supply Enable LDO7 Dual-voltage setting on LDO7 Channel 1 level shifter input Channel 2 level shifter input Channel 3 level shifter input LDO7 output voltage Channel 1 level shifter output Channel 2 level shifter output Channel 3 level shifter output Miscellaneous CREF GNDE DVA NC NC NC NC C7 D1 D4 D2 D3 C3 D6 IO Ground I Band gap decoupling Digital ground Dual-voltage setting for DC-DC, LDO2, LDO3
Figure 2. AT73C204 Pin Configuration in 49-ball BGA Package
1 A
VOUT5
2
3
4
5
6
7
GNDC
VINC
GNDD
VINB
VOUT3
GNDB
B
VOUT4 EN4 SWO VOUT2 EN2 VOUT1 VREF
C
LEDI LED0 NC EN5 SWI GNDF CREF
D
GNDE NC NC DVA CE NC VIND
E
VINF LSO3 VOUT7 LSI1 GNDG EN6 VOUT6
F
LSO1 LSO2 LSI2 DVB NC RESB LX
G
VINE LSI3 EN7 VOUT0 DM VINA GNDA
4
AT73C204
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AT73C204
Application Schematic
Figure 3. AT73C204 Application Schematic
VBAT E1 VINF D5 CE Reset Generator RESB F6
Application Processor
Main Control Unit
C1
LEDI
LED Driver
LEDO
C2 D1 F7 L1 G4 G7 B6 C3 C1
R1
VBAT
LX G6 D4 G5 VINA DVA DM Oscillator A5 B5 C10 C7 E5 B7 VINB EN2 CREF GNDG VREF SWI SWO GNDD VINC EN4 Open Drain Switch LDO3 2.4V/2.7V/2mA LDO4 2.8V/130mA VR VOUT2 LDO2 2.7V/2.8V/130mA VOUT3 GNDB VOUT4 LDO1 2.8V/130mA VOUT1 DC-DC Converter 1.9V/2.5V 300mA VOUT0 GNDA
VBAT
C11
C2
Memory Module
B4 C4
Camera Module
C5
A6 A7 B1 C6 C5
Power Device
e.g. Buzzer
B3 A4 A3 B2
Low-power Device
Bluetooth Module
VOUT5 C4 EN5 LDO5 2.8V/130mA GNDC
A1 A2 C7
WLAN Module
D7 E6
VIND EN6
LDO6 2.8V/130mA
VOUT6
E7 C8
MP3 Player Module
VOUT0 or VOUT1
G1 G3 F4 E4 F3 G2
VINE EN7 DVB LSI1 LSI2 LSI3 GNDE D6 F5 C3 D2 D3 D1 GNDF C6 Three-channel Level Shifter LSO1 LSO2 LSO3 F1 F2 E2 LDO7 1.8V/2.8V/10mA VOUT7 E3 C9
Audio Codec
Interface
5
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External Components Specifications
Table 2. External Component Specifications
Symbol R1 C1, C3, C4, C5, C6, C7, C8 C2 C9 C10 C11 L1 D1 Parameters 4.7 k, 1/8 W, 0603 2.2 F - X5R 6.3V/10%, 0603 22 F Tantale R, TYPEA 220 nF - X5R 10V/10%, 0603 10 nF - X5R 10V/10%, 0402 10 F - X5R 6.3V/10% 10 H HSMH - C670
6
AT73C204
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AT73C204
Functional Description
300 mA/1.9V/2.5V DC-toDC Converter for Co-processor Core
This DC-to-DC converter is a synchronous mode DC-to-DC "buck"-switched regulator using fixed- frequency architecture (PWM) and capable of providing 300 mA of continuous current. It has two levels of voltage programming for the co-processor core (1.9V or 2.5V). The operating supply range is from 3.1V to 4.2V, making it suitable for Li-Ion, Lipolymer or Ni-MH battery applications. This DC-to-DC converter is based on the pulse width modulation architecture to control the noise perturbation for switching noise sensitive applications (GSM). The operating frequency is set to 900 KHz using an internal clock, allowing the use of small surface inductor and moderate output voltage ripple. The controller consists of a reference ramp generator, a feedback comparator, the logic driver used to drive the internal switches, the feedback circuits used to manage the different modes of operation and the over-current protection circuits. An economic mode has been defined to reduce quiescent current. A low-dropout voltage regulator in parallel to the DC-to-DC converter minimizes standby current consumption during standby mode. Figure 4. Dual-power DC-to-DC Converter
VBAT DM
DC-to-DC Buck 1.9V or 2.5V 300 mA Internal FET
L
VOUT0
LDO 1.9V or 2.5V 10 mA Low Power
C
Low undershoot voltage is expected when going from PWM to LDO mode and viceversa. The circuit is designed in order to avoid any spikes when transition between two modes is enabled. Figure 5. Low-power/Full-power DC-to-DC Converter Transition
VOUT0
VOUT0
DM
High Power
Low Power
DM
High Power
Low Power
7
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Figure 6 shows typical efficiency levels of the DC-to-DC converter for several input voltages. Figure 6. DC-to-DC Converter with 1.9V Target Typical Case(1)
100 95 Efficiency (%) 90 85 80 75 70 0 50 100 150 200 250 300 350 400 Load Current (m A) VIN=3.1V VIN=3.6V VIN=4.2V
Note:
1. L = 10 H, ESR = 0.2 Ohm, c = 22 F, @ESR = 0.1 Ohm
LDO1, LDO3, LDO4, LDO5
The PSRR measures the degree of immunization against voltage fluctuations achieved by a regulator. An example of its importance is in the case of a GSM phone when the antenna switch activates the RF power amplifier (PA). This causes a current peak of up to 2A on the battery, with an important spike on the battery voltage. The voltage regulator must filter or attenuate this spike. Figure 7. Functional Diagram of LDO Single Mode
VBAT VINT
ON ON IBIAS VBG ON Pass Device VOUT GND GND Current Sensing and Limiter R1 GND VOUTS
ON
R2
ON
GND
8
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AT73C204
Figure 8 shows the Power Supply Rejection Ratio as functions of frequency and battery voltage. If a noise signal occurs at 1 kHz when the battery voltage is at 3V, the noise will be attenuated by 70 dB (divided by more than 3000) at the output of the regulator. Consequently, a 2V spike on the battery is attenuated to less than 1 mV, which is low enough to avoid any risk of malfunction by a device supplied by the regulator. Figure 8. Power Supply Rejection Ratio in Function of Frequency and Battery Voltage
P o w e r S u p p ly R e je ctio n Ra tio a t F u ll L o a d
P o w e r S u p p ly R e je ctio n R a ti o a t F u ll L o a d ve rsu s B a tte ry V o lta g e
10 -30 -35 -40 -45
100
1000
10000
100000
3.0 -30 3.5 4.0 4.5 5.0 5.5
V B A T = 3V
-40 -50 -60
P S RR [d B]
PSRR [ d B]
-50 -55 -60 -65 -70 -75 -80
Fr e q [ Hz ]
-70 -80 -90 -100 -110 -120
B a tte ry V o lta g e [V ]
V B A T = 4.25V V B A T = 5.5V
F req = 1 k Hz F req = 20 k Hz F req = 100 k Hz
F req = 100 Hz
LDO2, LDO6
The first approach to reducing standby current is to decrease the standby current inside the regulators themselves. Atmel achieves this by implementing a dual mode architecture where two output transistors are used in parallel as switches in the regulation loop. Figure 9 illustrates this architecture. Figure 9. Functional Diagram of LDO Dual Mode
VBAT
ON LP ON LP
V BG ON
V BG ON
GND
VOUT
GND
ON LP
Current Sensing and Limiting
VOUTS R1
GND
R2 ON IBIAS ON, LP
GND
GND
9
6014A-PMGMT-10/03
In Figure 9, the left-hand output transistor is sized large enough for the required output current under full load, for example, 100 mA. In order to achieve a sufficient margin of stability, the current sensing block uses a bias cell where the current consumption is linked to the required output current. The higher the output current, the higher the bias current needed to stabilize the loop. The right-hand output transistor delivers a very small output current, typically less than 1 mA, sufficient only to maintain the output voltage with enough current to cover the leakage current of the supplied device. This requires a much smaller bias current and, consequently, a smaller standby current inside the regulator.
LDO7 Temperature Sensor
This regulator has extremely low quiescent current and is suited where power supply is enabled almost all the time. Typical use could be the supply of back-up battery. The temperature sensor voltage output is a linear function of temperature. The temperature seen by the sensor is directly related to the chip activity and the power internally dissipated. To get a good indication of the ambient temperature, the software must take into account this offset.
Three-channel Level Shifters
This block provides a DC-to-DC or Memory Card level shifter and specific ESD protections. Signals are level-shifted on the LDO2 supply, allowing dual-voltage option: 1.8V or 2.8V. If the memory type is Subscriber Identity Module (SIM) Card, level shifters are compliant with ETSI GSM11.12 & 11.18.
Absolute Maximum Ratings
Operating Temperature (Industrial)............... -40C to +85C Storage Temperature ................................. -55C to + 150C Power Supply Input VINA, VINB,...,VINF ............................................ -0.3V to +6.5V I/O Input (all except to power supply........ -0.3V to VMAX+0.3 *NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Table 3. Recommended Operating Conditions
Parameter Operating Temperature Power Supply Input VINA, VINB,..., VINF Conditions Min -20 3.0 Maw 85 4.5 Unit C V
10
AT73C204
6014A-PMGMT-10/03
AT73C204
Electrical Characteristics
VOUT0
Table 4. VOUT0 Electrical Characteristics
Symbol VINA VOUT0 VOUT0 IOUT0 ISD EFF VDCLD VTRLD VDCLE VTRLE VOUT0 VOUT0 IOUT0 VDROP IQC VDCLD VTRLD VDCLE VTRLE PSRR VLPFP VFPLP Parameter Operating Supply Voltage Output Voltage Output Voltage Output Current Shutdown Current Efficiency Static Load Regulation Transient Load Regulation Static Line Regulation Transient Line Regulation Output Voltage Output Voltage Output Current Dropout Voltage Quiescent Current Static Load Regulation Transient Load Regulation Static Line Regulation transient Line Regulation Ripple Rejection Overshoot Voltage Undershoot Voltage IOUT = 10 mA to 200 mA @1.9V Full-power Mode (10% to 90% of IOUT(MAX) Full-power Mode (10% to 90% of IOUT(MAX),TR = TF = 5s Full-power Mode (10% to 90% of IOUT(MAX), 3.2V to 4.2V) Full-power Mode (10% to 90% of IOUT(MAX), 3.2V to 4.2V) Low-power Mode (DVA = 0, DM = 1) Low-power Mode (DVA = 1, DM = 1) Low-power Mode (DM = 1) Low-power Mode (DM = 1) Low-power Mode (DM = 1) Low-power Mode (0 to 10 mA) Low-power Mode (0 to 10 mA), TR = TF = 5s Low-power Mode (3.2V to 4.2V) Low-power Mode (3.2V to 4.2V) Low-power Mode up to 1 KHz Voltage drop from Low-power to Full-power Voltage drop from Low-power to Full-power -15 40 45 0 0 10 11 1.75 2.35 Full-power (DVA = 0, DM = 0) Full-power (DVA = 1, DM = 0) Full-power (DM = 0) Conditions Min 3 1.80 2.45 1.90 2.50 300 0.1 90 50 50 20 35 1.85 2.40 1.95 2.45 10 400 14 50 10 8 15 Typ Max 5.5 2.0 2.55 400 1 Unit V V V mA A % mV mV mV mV V V mA mV A mV mV mV mV dB mV mV
11
6014A-PMGMT-10/03
LDO2
Table 5. LDO2 Electrical Characteristics
Symbol VINB VOUT2 VOUT2 VINT IOUT2 IQC DVOUT DVPEAK DVOUT Parameter Operating Supply Voltage Output Voltage Output Voltage Internal Supply Voltage Output Current Quiescent Current Line Regulation Line Regulation Transient Load Regulation VBAT: 3V to 3.4V, IOUT = 130 mA Same as above, TR = TF = 5 s 10% - 90% IOUT, VBAT = 3V 10% - 90%IOUT, VBAT = 5.0V 10% - 90% IOUT, VBAT = 5.5V DVPEAK PSRR VN TR ISD Load Regulation Transient Ripple rejection Output Noise Rise Time Shut Down Current Same as above, TR = TF = 5 s F = 217Hz - VBAT = 3.6V BW: 10 Hz to 100 kHz 100% IOUT, 10% - 90% VOUT DVA = 0 DVA = 1 Conditions Min 3 2.65 2.75 2.4 80 195 3 4 10 15 15 15 70 29 50 1 2.70 2.80 Typ Max 5.5 2.75 2.85 2.6 130 236 Unit V V V V mA A mV mV mV mV mV mV dB VRMS s A
12
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AT73C204
LDO1
Table 6. LDO1 Electrical Characteristics
Symbol VINB VOUT1 IOUT1 IOUT IQC IQC DVOUT DVPEAK Parameter Operating Supply Voltage Output Voltage Full Power Mode Output Current Full Power Mode Output Current Low Power Mode Quiescent Current FP Mode Quiescent Current LP Mode Line Regulation FP Mode VBAT: 3.4V to 3V, IOUT = 80 mA 25 9.75 30 11.5 Conditions Min 3 2.74 2.80 50 Typ Max 5.5 2.86 80 10 36 13.75 1 3 Unit V V mA mA A A mV mV
Line Regulation Transient FP Mode VBAT: from 5V to 5.4V and from 3.4V to 3V, IOUT = 80 mA, TR = TF = 5 s Line Regulation LP Mode VBAT: 3.4V to 3V, IOUT = 5 mA
DVOUT DVPEAK
3 4
mV mV
Line Regulation Transient LP Mode VBAT: from 5V to 5.4V and from 3.4V to 3V, IOUT = 5 mA, TR = TF = 5 s Load Regulation FP Mode From 0 to 80mA and from 90% to 10% IOUT(MAX), VBAT = 3.4V
DVOUT DVPEAK
3 (4 at 5.5V) 23
mV mV
Load Regulation Transient FP Mode From 0 to IOUT(MAX) and from 90% to 10% IOUT(MAX), TR = TF = 5 s, VBAT = 3.4V Load Regulation LP Mode Ripple Rejection Output Noise FP mode Output Noise LP Mode Rise Time FP Rise Time LP Shut Down Current Operating Supply Voltage Internal Operating Supply Voltage Short Circuit Current 3 2.74 2.8 50 From 0 to 80mA and from 90% to 10% IOUT(MAX), VBAT = 3.4V F = 217Hz BW: 10 Hz to 100 kHz BW: 10 Hz to 100 kHz IOUT = IOUT(MAX) IOUT = IOUT(MAX) 70 50 40 45
DVOUT PSRR VN VN TR TR ISD VBAT VSAUV ISC
5 (10 at 5.5V)
mV dB
80 300 130 170 1 5.5 2.86 80
VRMS VRMS s s A V V mA
13
6014A-PMGMT-10/03
LDO3
Table 7. LDO3 Electrical Characteristics
Symbol VINB VOUT3 VOUT3 IOUT3 VDROP IQC PSRR TR Parameter Operating Supply Voltage Output Voltage Output Voltage Output Current Dropout Voltage Quiescent Current Ripple Rejection Rise Time 110 4.8 6.6 40 320 BB1 = 0 BB1 = 1 Conditions Min 3 2.4 2.65 2.45 2.70 2 Typ Max 5.5 2.50 2.75 5 50 9.7 Unit V V V mA mV A dB s
Buffered Voltage Reference
Table 8. Buffered Voltage Reference Electrical Characteristics
Symbol VREF IREF VDROP IQC ISD PSRR TR Parameter Output Voltage Output Current Dropout Voltage Quiescent Current Shutdown Current Ripple Rejection Rise time 110 4.8 6.6 0.1 40 320 Conditions Min 1.45 Typ 1.50 Max 1.55 0.5 50 9.7 1 Unit V mA mV A A dB s
14
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AT73C204
LDO4, LDO5, LDO6
Table 9. LDO4, LDO5, LDO6 Electrical Characteristics
Symbol VINC VINT VOUT IOUT IQC DVOUT DVPEAK DVOUT Parameter Operating Supply Voltage Operating Internal Supply Voltage Output Voltage Output Current Quiescent Current Line Regulation Line Regulation Transient Load Regulation VBAT: 3V to 3.4V, IOUT = 130 mA Same as above, TR = TF = 5 s 10% - 90% IOUT, VBAT = 3V 10% - 90% IOUT, VBAT = 5.0V 10% - 90% IOUT, VBAT = 5.5V DVPEAK PSRR VN TR ISD Load Regulation Transient Ripple Rejection Output Noise Rise Time Shut Down Current Same as above, TR = TF = 5 s F=217Hz - VBAT = 3.6V BW: 10 Hz to 100 kHz 100% IOUT, 10% - 90% VOUT 70 Conditions Min 3 2.4 2.74 2.5 2.8 80 195 3 4 10 15 15 1.2 73 29 37 50 1 Typ Max 5.5 2.6 2.86 130 236 2 2.85 1 1 1 2.4 Unit V V V mA A mV mV mV mV mV mV dB VRMS s A
Open Drain Switch
Table 10. Open Drain Switch Electrical Characteristics
Symbol VOL IOL TON TOFF Parameter Low Output Voltage Low Output Current Turn-on Time Turn-off Time Conditions IOL = 100 mA Min Typ Max 0.4 100 10 10 Unit V mA s s
15
6014A-PMGMT-10/03
LDO7
Conditions are VINE = 1.8V or 2.8V, tA = -40C to +85C, CDVCC = 100 nF, CSIM-VCC = 100 nF Table 11. LDO7 Electrical Characteristics.
Symbol VINE VOUT7 Parameter Operating Supply Voltage Output Voltage Conditions VOUT0 or VOUT1 IOUT7 < 10 mA EN7 = 1 DVB = 1 IOUT7 < 10mA EN7 = 1 DVB = 0 EN7 = 0 Low-power Mode Full-power Mode 10 40 Min 1.65 1.71 1.8 1.89 V Typ Max Unit
VOUT7
Output Voltage
2.74
2.8
2.86
V
ISD IQC IQC IOUT7 ISC
Total Shutdown Current Quiescent Current Quiescent Current Output Current Short Circuit Current
0.1 8
1 9.5 60
A A A mA mA
16
AT73C204
6014A-PMGMT-10/03
AT73C204
Packaging Information
Figure 10. Mechanical Package Drawing for 49-ball Ball Grid Array
0.65
0.26
0.30
0.53
17
6014A-PMGMT-10/03
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6014A-PMGMT-10/03

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